NAR-3358 Industrial Linux SiP | Corezzle Electronics

Generative Hardware, SiP, Edge AI & IoT Solutions

NAR-3358-1G-TCE · T-SiP (BGA) · 30 × 30 mm

CA-32MP2x-16GB-BGA

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Prototype Stage · Sample Program. The NAR-3358 is currently in the prototype stage; volume production is planned for September 2026. You can submit a request for samples and an engineering kit for early evaluation. The detailed datasheet and reference design are shared upon request.

NAR-3358 is a System-in-Package module in a 30 × 30 mm T-SiP (BGA, 400 balls) package, designed for industrial automation and embedded system applications. It integrates the TI Sitara AM3358 processor (ARM® Cortex®-A8 @ 1 GHz, NEON SIMD, PowerVR SGX530 3D GPU, and 2× PRU-ICSS real-time cores), 1 GB DDR3L system memory (16-bit EMIF, 800 MT/s), 4 GB eMMC 5.0 storage, a dual power management architecture (TPS65217C main PMIC + TL5209 secondary LDO), and in-package clock sources (24 MHz main, 32.768 kHz RTC) in a single package. It meets industrial connectivity needs with USB OTG, Ethernet MII, MMC/SD, GPMC, McASP, CAN, LCD, and ADC interfaces; it supports Yocto Linux and Android, and is compatible with the mainline Linux + Yocto BSP open-source ecosystem. By consolidating dozens of discrete components into a single SiP, the NAR-3358 reduces board space and design complexity; it is optimized for edge gateway, HMI, and industrial control applications. It is offered as a standard SiP, with a project-based design service provided for custom SiP variants.

Product Details

Block Diagram

Select diagram:

NAR-3358 SiP Module Block Diagram

NAR-3358 SiP Module Block Diagram

Integrated Components

Processor and Microcontroller

Application Processor

  • Processor: TI Sitara AM3358 · ARM Cortex-A8 @ 1 GHz · NEON SIMD
  • Graphics / acceleration: PowerVR SGX530 3D GPU
  • Real-time: 2× PRU-ICSS programmable co-processors (200 MHz)

Memory and Storage

DDR3L / eMMC / EEPROM

  • System memory: 1 GB DDR3L (16-bit EMIF, 800 MT/s)
  • Storage: 4 GB eMMC 5.0 (HS200 / HS400)
  • Board ID: 4 KB I²C EEPROM (board ID, 24LC32)

Power Management

Dual PMIC

  • Main PMIC: TPS65217C · Li-Ion charging + 3× DCDC + 4× LDO
  • Secondary PMIC: TL5209 · 1 A LDO 1.8 V (analog island supply)

Timing and Reset

Clock / Reset

  • Main clock: 24 MHz crystal (in-package, internal)
  • RTC clock: 32.768 kHz crystal (in-package, internal)
  • Reset: SN74LVC1G07 reset buffer

Features

Hardware Specifications

  • 30 × 30 mm T-SiP (BGA), 400 balls (20×20), 1.27 mm pitch
  • ARM Cortex-A8 @ 1 GHz + NEON SIMD
  • PowerVR SGX530 3D GPU
  • 2× PRU-ICSS real-time co-processors (200 MHz)
  • 1 GB DDR3L system memory (16-bit EMIF)
  • 4 GB eMMC 5.0 onboard storage
  • Dual PMIC power architecture (TPS65217C + TL5209), Li-Ion charging
  • In-package clock sources (24 MHz main + 32.768 kHz RTC)
  • Operating temperature: −40 / +85 °C (industrial, preliminary)
  • Typical power consumption: bench measurement pending (TBD)

Software Features

  • Yocto Linux BSP (kernel, drivers, board support package)
  • Android support (AOSP integration)
  • Mainline Linux kernel + device tree support
  • Debian community compatibility
  • OTA update support
  • SDK and example projects (C, Python)

Compatibility

  • TI Sitara AM335x reference-compatible
  • Open-source ecosystem compatible with the Yocto Linux Project
  • Android Open Source Project (AOSP) compatible
  • Positioned for mainline Linux + Yocto BSP
  • Expandable with an evaluation kit

Interfaces

  • USB 2.0 OTG (480 Mbps, High-Speed)
  • Ethernet MII (10 / 100)
  • MMC / SD / SDIO
  • GPMC (General-Purpose Memory Controller)
  • McASP (Multichannel Audio Serial Port)
  • CAN (industrial communication)
  • UART, SPI, I²C (peripheral connectivity)
  • LCD (parallel RGB display interface)
  • ADC (differential reference VREFP / VREFN)
  • eCAP / ePWM / eQEP (motor control / timers)
  • JTAG (debug)

Development Environment

  • Corezzle SDK · development package for Yocto + Android
  • Evaluation board (with USB, Ethernet, LCD connectors)
  • Mainline Linux + Yocto BSP toolchain
  • Sample device tree (DTB) and reference configuration

Documentation

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